Semiconductor processing dispatch control

ABSTRACT

An embodiment is a method for semiconductor processing control. The method comprises identifying a key process stage from a plurality of process stages based on a parameter of processed wafers, forecasting a trend for a wafer processed by the key process stage and some of the plurality of process stages based on the parameter, and dispatching the wafer to one of a first plurality of tools in a tuning process stage. The one of the first plurality of tools is determined based on the trend.

This application is a divisional of U.S. patent application Ser. No. 12/839,014, filed on Jul. 19, 2010, entitled “Semiconductor Processing Dispatch Control,” which application is hereby incorporated herein by reference in its entirety.

TECHNICAL FIELD

The present disclosure relates generally to a system and method for semiconductor processing control and, more particularly, to a system and method for semiconductor processing dispatch control.

BACKGROUND

Generally, semiconductor wafers go through many processing steps before a completed die is formed. Some of these processing steps may include lithography, etching, doping, and depositing different materials. The quality of the completed die may depend largely on the accuracy and precision of the processing between different processing steps. For example, misalignment of a gate structure, imprecise doping concentrations, or dielectric layers that are too thick or thin may cause an undesirable amount of leakage current in a transistor or delay in the operation of the circuit.

Further complicating this problem may be a semiconductor manufacturer's desire to maximize the number of dies produced by the processing steps. In an attempt to maximize productivity, a manufacturer may provide many tools for each processing step. However, each tool may have a behavior different from other tools within the particular processing step. Accordingly, coordinating processing between different tools in different steps may be difficult.

One typical method for coordinating processing includes dispatching lots from tools to specified respective tools in a subsequent stage to compensate for previous processing. This method may consider only the in-line performance of each tool rather than the final quality of the completed product. Further, this method may also suffer from productivity drawbacks because lots from a first tool in a stage are automatically dispatched to a second tool in a subsequent stage without regard for the availability of the second tool.

Another typical method attempts to control tool behavior and does not have any set dispatching rules. One example is an Automatic Process Control (APC) that uses in-line measurements after processing a lot to control the tool that previously processed the lot and to control the tool that will immediately subsequently process the lot. This method may consider only productivity, such as minimizing tool idle time, and may ignore the mismatch impact between tools. Thus, the quality of a finished die may be adversely impacted.

SUMMARY

An embodiment is a method for semiconductor processing control. The method comprises identifying a key process stage from a plurality of process stages based on a parameter of processed wafers, forecasting a trend for a wafer processed by the key process stage and some of the plurality of process stages based on the parameter, and dispatching the wafer to one of a first plurality of tools in a tuning process stage. The one of the first plurality of tools is determined based on the trend.

Another embodiment is a computer program product for providing semiconductor processing control, and the computer program product has a medium with a computer program embodied thereon. The computer program comprises computer program code for providing a first data set for first measured results for a first parameter of processed wafers and a second data set for second measured results for a second parameter of the processed wafers. The first data set comprises first subsets, and the second data set comprises second subsets. Each first subset and each second subset corresponds to one tool in a processing line, and the processing line comprises multiple tools and multiple stages.

The computer program further comprises computer program code for determining a first residual model and a second residual model for each first subset and each second subset, respectively, and computer program code for determining a first residual vector and a second residual vector for each first subset and each second subset, respectively. A first residual vector entry is based on the first residual model and one of the first measured results of the respective first subset, and a second residual vector entry is based on the second residual model and one of the second measured results of the respective second subset.

The computer program further comprises computer program code for determining a first residual average and a first residual standard deviation of the first residual vector for each first subset, and a second residual average and a second residual standard deviation of the second residual vector for each second subset, such that each of the multiple tools has a corresponding first residual average, first residual standard deviation, second residual average, and second residual standard deviation. The computer program further comprises computer program code for, for each of the multiple stages, determining an overall index based on the first residual average, the first residual standard deviation, the second residual average, and the second residual standard deviation for each of the multiple tools in the respective stage.

The computer program further comprises computer program code for identifying at least one of the multiple stages as a key process stage when the at least one of the multiple stages has a corresponding overall index greater than a threshold, and comprises computer program code for forecasting a trend of a wafer based on routing of the wafer through some of the multiple stages through the key process stage. The computer program further comprises computer program code for dispatching the wafer to one of the multiple tools in at least one stage of the multiple stages subsequent to the key process stage in the processing line based on the trend.

A yet further embodiment is a system for semiconductor processing. The system comprises a processing line comprising a key process stage and a tuning process stage, a tool effect module operable to determine tool effects on an electrical parameter for tools in the key process stage and for tools in the tuning process stage, a trend forecast module operable to determine a trend of the electrical parameter of a wafer that has been processed through the key process stage, and a dispatch control module operable to determine a tuning tool in the tuning process stage that optimally compensates for the trend of the electrical parameter of the wafer and to dispatch the wafer to the tuning tool. The key process stage most affects the electrical parameter of a finished product, and the tuning process stage is subsequent the key processing stage in the processing line.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present embodiments, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a system for semiconductor processing and for performing a method of semiconductor processing control;

FIG. 2 is a method of semiconductor processing control;

FIG. 3 is an exemplary method for determining a tool effect to identify a key process stage;

FIG. 4 is an exemplary method for clustering tools within a stage;

FIG. 5 is an exemplary method for forecasting a wafer and/or lot trend based on routing history;

FIG. 6 is a method for dispatching the wafer and/or lot for a tuning process;

FIG. 7A is an example of results of a prioritization considering lots that are being processed independently and of routing in a tuning process;

FIG. 7B is an example of results of a prioritization considering all lots that are being processed simultaneously and of routing in a tuning process; and

FIG. 8 is a block diagram of a processor based system.

DETAILED DESCRIPTION OF ILLUSTRATIVE EMBODIMENTS

The making and using of the present embodiments are discussed in detail below. It should be appreciated, however, that the present disclosure provides many applicable inventive concepts that can be embodied in a wide variety of specific contexts. The specific embodiments discussed are merely illustrative of specific ways to make and use the disclosed subject matter, and do not limit the scope of the different embodiments.

Contemplated embodiments include a system for semiconductor processing, such as depicted in FIG. 1, and a method of semiconductor processing control, such as shown in FIG. 2. The system may be capable of performing the method of semiconductor processing control. Generally, the method may comprise, as shown in FIG. 2, determining a tool effect to identify a key process stage (Step 100), optionally, clustering tools within a stage (Step 200), forecasting a wafer and/or lot trend based on routing history (Step 300), and dispatching the wafer and/or lot for a tuning process (Step 400). Details of this method and the system for implementing this method are described below, wherein Step 100 is discussed with reference to FIG. 3, Step 200 is discussed with reference to FIG. 4, Step 300 is discussed with reference to FIG. 5, and Step 400 is discussed with reference to FIG. 6. However, a person having ordinary skill in the art will understand various modifications of these embodiments which are contemplated to be within the scope of other embodiments.

FIG. 1 illustrates a system 10 for semiconductor processing and for performing a method of semiconductor processing control according to an embodiment. The system 10 comprises a key process stage 12, a key in-line measurement device 14, a tuning process stage 16, and a wafer acceptance testing (WAT) and circuit performance testing (CP) device 18. Process flows 40, 42, and 44 depict the routing of a wafer and/or lot between the key process stage 12, key in-line measurement device 14, tuning process stage 16, and WAT/CP device 18 during processing in the system 10.

The system 10 further comprises an in-line model module 20, a tool cluster and effect (TCE) determination module 22, a dispatching control engine module 24, a trend forecasting module 26, and a routing data for wafer and/or lot under processing module 28. Control flows 46, 48, 50, 52, and 54 depict various data and control signals that are passed between various modules and devices for clustering, forecasting, and dispatching, for example. Data flows 56, 58, 60, 62, and 64 indicate the flow of data between different modules and devices for modeling and different determinations, for example. Dispatching control flow 66 depicts the flow of data for dispatching a wafer and/or lot for the tuning process stage 16. The data and control signals that are passed along the various flows will be explained in more detail in conjunction with other aspects of embodiments.

FIG. 3 is an exemplary method for determining a tool effect to identify the key process stage, as in Step 100 illustrated in FIG. 2. Details of the methods of FIGS. 3 through 6 will be discussed with reference to the system 10 of FIG. 1. Step 102 of FIG. 3 includes measuring a parameter or multiple parameters of wafers and/or lots. This measuring may be performed by the WAT/CP device 18. Exemplary parameters include leakage current of a device (IDDQ) and the delay of a device (P-delay), which will be used in later descriptions as examples for different embodiments. Various numbers of parameters and different parameters may be used in other embodiments.

Step 104 includes modeling each parameter as a function of a device parameter and a tool effect by using the measured parameter for each wafer and/or lot processed by a tool. For clarity, it should be noted that, even though not specifically depicted in FIG. 1, a manufacturing process may include numerous different stages and each stage may include multiple tools. Step 104 may be performed individually for each tool within the manufacturing process. With reference to FIG. 1, the WAT/CP device 18 may provide the measured parameter(s) to the in-line model module 20 by data flow 58. The in-line model module 20 may then create a model for each parameter, as described in step 104. For example, for a tool-1 in stage-2, the in-line model module 20 may collect a plurality of the measured values of IDDQ for wafers and/or lots processed by tool-1 in stage-2. Then, the in-line model module 20 may create a model for IDDQ using linear regression. The linear regression may define IDDQ as a function of a first coefficient times a PMOS saturation current, plus a second coefficient times a NMOS saturation current, plus the tool effect offset, i.e. IDDQ=A₁I_(D,satPMOS)+A₂I_(D,satNMOS)+C.

Step 106 includes using the function defined in step 104 to determine the tool effect, or residual, for each wafer and/or lot processed by the tool. The in-line model module 20 may determine the residual according to step 106. Continuing with the preceding example, the linear regression model may be manipulated to solve for the residual C , i.e. C=IDDQ−A₁I_(D,satPMOS)−A₂I_(D,satNMOS).

Step 108 includes determining an average and a standard deviation of the tool effect for each parameter corresponding to each tool. The in-line model module 20 may provide the residual to the TCE determination module 22 by control flow 46. The WAT/CP device 18 may provide the parameter measurements to the TCE determination module 22 by data flow 62. The TCE determination module 22 may use the residual and the measured parameter for each wafer and/or lot processed by the tool to determine a calculated tool effect corresponding to the parameter. The TCE determination module 22 may create a vector containing calculated tool effect entries, where each calculated tool effect entry corresponds to a measured wafer and/or lot. Further continuing the preceding example, individual entries for the calculated tool-1 effect vector for IDDQ may be determined using the residual C with the modeled coefficients A₁ and A₂ and the measured IDDQ, I_(D,satPMOS), and I_(D,satNMOS) for an individual wafer and/or lot processed by tool-1. Similarly, a tool-1 effect vector for P-delay may be determined.

Once the tool effect vector corresponding to the parameter is compiled, an average μ and a standard deviation σ of the tool effect for each parameter may be determined. Although many different means of calculating the average μ and standard deviation σ are available, one technique TCE determination module 22 may use is a standard deviational ellipse method when multiple parameters are used to determine the tool effect. The standard deviation ellipse may transform the tool effect vectors for multiple parameters into a spatial ellipse encompassing at least, for example, ninety-five percent of the entries, where each parameter corresponds to an axis of the ellipse. Based on the ellipse, the average μ and standard deviation σ of the tool effect for each parameter may be calculated. Persons having ordinary skill in the art will readily understand this computation, and as such, explicit discussion of the computation herein is omitted for brevity. Continuing the above example, first entries in the tool-1 effect vector for IDDQ and the tool-1 effect vector for P-delay should correspond to measurements of a first wafer and/or lot, second entries of the vectors should correspond to measurements of a second wafer and/or lot, and so on. The P-delay parameter may serve as an x-axis and the IDDQ parameter may serve as the y-axis for a distribution of entries. The distribution may then be transformed into an ellipse, and an average μ₁ and standard deviation σ₁ of the tool-1 effect for IDDQ and an average μ_(P) and standard deviation σ_(P) of the tool-1 effect for P-delay may be determined from the ellipse.

It should further be noted that steps 104, 106, and 108 may be carried out individually for each tool in each stage. For example, in the above example, stage-2 may comprise a tool-1, a tool-2, and a tool-3. For each tool, an average μ₁ and standard deviation σ₁ of the tool effect for IDDQ and an average μ_(P) and standard deviation σ_(P) of the tool effect for P-delay may be determined. The average and standard deviation of the tool-1 effect for IDDQ may be noted as μ_(1,1) and σ_(1,1), respectively, and the tool-2 effect for IDDQ may be noted as μ_(1,2) and σ_(1,2). A generic notation is that for tool k, the average and standard deviation of the tool effect for IDDQ and an average and standard deviation of the tool effect for P-delay may be noted as μ_(1,k), σ_(1,k), μ_(P,k), and σ_(P,k), respectively.

Step 110 includes defining an overall index for each stage in processing by using a weighted average and weighted standard deviation of the tool effect for each parameter corresponding to each tool within the stage. The TCE determination module 22 may determine the overall index by calculating the weighted average of the pair-wise distances between the weighted averages of the parameter or multiple parameters plus the weighted average of the pair-wise distances of the weighted variances of the parameter(s) for each stage.

Step 110 may be illustrated by continuing the above example. Define vectors μ_(X) and σ_(X) for N tools in stage X as

$\mu_{X} = \begin{bmatrix} \mu_{k}^{X} \\ \mu_{k + 1}^{X} \\ \vdots \\ \mu_{N}^{X} \end{bmatrix}$ and

$\sigma_{X} = \begin{bmatrix} \sigma_{k}^{X} \\ \sigma_{k + 1}^{X} \\ \vdots \\ \sigma_{N}^{X} \end{bmatrix}$ where, for tool k in stage X, μ_(k) ^(X)=(μ_(1,k) ^(X), μ_(P,k) ^(X)) and σ_(k) ^(X)=(σ_(1,k) ^(X), σ_(P,k) ^(X)). Further, define weighted vectors μ_(X) and σ_(X) for N tools in stage X as

$\overset{\_}{\mu_{X}} = \begin{bmatrix} \overset{\_}{\mu_{k}^{X}} \\ \overset{\_}{\mu_{k + 1}^{X}} \\ \vdots \\ \overset{\_}{\mu_{N}^{X}} \end{bmatrix}$ and

$\overset{\_}{\sigma_{X}} = \begin{bmatrix} \overset{\_}{\sigma_{k}^{X}} \\ \overset{\_}{\sigma_{k + 1}^{X}} \\ \vdots \\ \overset{\_}{\sigma_{N}^{X}} \end{bmatrix}$ where, for tool k, μ_(k) ^(X) =(ω₁μ_(1,k) ^(X), ω₂μ_(P,k) ^(X)) and σ_(k) ^(X) =(ω₃σ_(1,k) ^(X), ω₄σ_(P,k) ^(X)). It should be noted for clarity that superscript X is a stage identifier and not an exponent. The overall index OI_(X) for stage X may be defined as the weighted average of the pair-wise distances between the weighted averages μ_(X) plus the weighted average of the pair-wise distances between the weighted standard deviations σ_(X) . Mathematically, this is represented by equation (1) below. OI _(X)( μ_(X) , σ_(X) |i, j>i)=ω_(μ) E└D( μ_(i) ^(X) , μ_(j) ^(X) )┘+ω_(σ) E└D( σ_(i) ^(X) , σ_(j) ^(X) )┘  Eq.(1) A long-hand example for determining the overall index OI_(X) of a stage-2, i.e. X=2, comprising tool-1, tool-2, and tool-3, i.e. N=3, is show below in equation (2), according to the definition in equation (1).

$\begin{matrix} {{OI}_{2} = {{\frac{w_{\mu}}{3} \times \begin{bmatrix} {\sqrt{\left( {{w_{1}\mu_{I,1}^{2}} - {w_{1}\mu_{I,2}^{2}}} \right)^{2} + \left( {{w_{2}\mu_{P,1}^{2}} - {w_{2}\mu_{P,2}^{2}}} \right)^{2}} +} \\ {\sqrt{\left( {{w_{1}\mu_{I,1}^{2}} - {w_{1}\mu_{I,3}^{2}}} \right)^{2} + \left( {{w_{2}\mu_{P,1}^{2}} - {w_{2}\mu_{P,3}^{2}}} \right)^{2}} +} \\ \sqrt{\left( {{w_{1}\mu_{I,2}^{2}} - {w_{1}\mu_{I,3}^{2}}} \right)^{2} + \left( {{w_{2}\mu_{P,2}^{2}} - {w_{2}\mu_{P,3}^{2}}} \right)^{2}} \end{bmatrix}} + {\frac{w_{\sigma}}{3} \times \begin{bmatrix} {\sqrt{\left( {{w_{3}\sigma_{I,1}^{2}} - {w_{3}\sigma_{I,2}^{2}}} \right)^{2} + \left( {{w_{4}\sigma_{P,1}^{2}} - {w_{4}\sigma_{P,2}^{2}}} \right)^{2}} +} \\ {\sqrt{\left( {{w_{3}\sigma_{I,1}^{2}} - {w_{3}\sigma_{I,3}^{2}}} \right)^{2} + \left( {{w_{4}\sigma_{P,1}^{2}} - {w_{4}\sigma_{P,3}^{2}}} \right)^{2}} +} \\ \sqrt{\left( {{w_{3}\sigma_{I,2}^{2}} - {w_{3}\sigma_{I,3}^{2}}} \right)^{2} + \left( {{w_{4}\sigma_{P,2}^{2}} - {w_{4}\sigma_{P,3}^{2}}} \right)^{2}} \end{bmatrix}}}} & {{Eq}.\mspace{14mu}(2)} \end{matrix}$

Weights, such as weights ω_(μ), ω_(σ), ω₁, ω₂, ω₃, and ω₄, may be determined through an iterative trial and error process. The weights may be valued so as to place a higher priority or weight on the parameter(s) that most affect the quality of a finished product. For example, if the parameter that causes the most defective dies is the average of IDDQ, then weight ω₁ may be larger than the other weights. Further as an example, if the deviation of the P-delay is the greatest factor, then weight ω₄ may be larger than the other weights. Another constraint on the weights may include a soft constraint that maintains maximum correlation weighting with respect to a desired final target, such as yield or WAT/CP.

Step 112 includes identifying a key processing stage based on the overall indexes of each stage. The TCE determination module 22 may compare the overall indexes of the stages to determine if any overall index is above a defined threshold. For an overall index above the threshold, the stage corresponding to the overall index may be identified as a key process stage 12. Also, the TCE determination module 22 may identify a stage subsequent to the identified key process stage 12 in the manufacturing flow as a tuning process stage 16. For example, assume that a manufacturing process comprises sequential stage-1, stage-2, and stage-3, and that the overall index for stage-2 OI₂ is over the threshold. Stage-2 may be identified as a key process stage. Further, subsequent stage-3 may be identified as a tuning process stage.

FIG. 4 is an exemplary method for clustering tools within a stage, as in Step 200 illustrated in FIG. 2. Step 202 includes determining pair-wise distances between the averages and/or standard deviations of the tool effect for the parameter(s) for pairs of tools within a stage. Step 204 includes clustering pairs of tools, a tool with another cluster, or pairs of clusters within the stage that have a minimized pair-wise distances. Step 206 includes repeating steps 202 and 204 until the minimized pair-wise distance is greater than a defined threshold. The TCE determination module 22 may perform steps 202, 204, and 206 for easier handling of the number of tools. The clustering may be said to be agglomerative and may be visually represented by a dendrogram. Persons having ordinary skill in the art will readily understand that there are many versions of agglomerative clustering, and each version is contemplated as being within the scope of different embodiments. Further, other clustering methods are considered within the scope of embodiments, such as K-centering clustering.

FIG. 5 is an exemplary method for forecasting a wafer and/or lot trend based on routing history, as in Step 300 illustrated in FIG. 2. Step 302 includes identifying the routing of a wafer and/or lot during processing through the identified key process stage. The routing data for wafer and/or lot under processing module 28 may provide the routing data that identifies the routing of the wafer and/or lot to the trend forecasting module 26 by data flow 64. The wafer and/or lot may be dispatched through various different routes through the identified key process stage 12. For example, in a manufacturing process that comprises three stages, stage-1, stage-2, and stage-3, with each stage comprising three tools, tool-1, tool-2, and tool-3, if stage-2 is identified as a key process stage 12, a wafer and/or lot may be dispatched through one of nine different routes through stage-2. If the wafer and/or lot is dispatched to stage-1 tool-2 and to stage-2 tool-3, this routing information may be sent to the trend forecasting module 26.

Step 304 includes identifying the average and standard deviation of the tool effect for the parameter(s) for each tool, or representative tool cluster, in the routing that processed the wafer and/or lot. The TCE determination module 22 may receive data from the key process stage 12 via control flow 50 and may provide the average and standard deviation of the tool effect for the parameter(s) being used in the process to the trend forecasting module 26 by control flow 52. The trend forecasting module 26 may identify the averages and standard deviations for the tools or representative tool clusters that processed the wafer and/or lot during the different stages by use of the routing data provided by the routing data for wafer and/or lot under processing module 28. For example, assume the three stage process above with stage two being a key process stage 12, and assume the parameters used are IDDQ and P-delay as discussed above. The TCE determination module 22 may provide the averages and standard deviations for IDDQ and P-delay for stage-1 tool-1, stage-1 tool-2, stage-1 tool-3, stage-2 tool-1, stage-2 tool-2, and stage-2 tool-3, i.e. vectors μ₁, σ₁, μ₂, and σ₂. From vectors μ₁, σ₁, μ₂, and σ₂, the trend forecasting module 26 may identify the averages and standard deviations of IDDQ and P-delay for stage-1 tool-2 from vectors μ₁ and σ₁, i.e. μ₂ ¹=(μ_(1,2) ¹, μ_(P,2) ¹) and σ₂ ¹=(σ_(1,2) ¹, σ_(P,2) ¹) based on the routing data, and may identify the averages and standard deviations of IDDQ and P-delay for stage-2 tool-3 from vectors μ₂ and σ₂, i.e. μ₃ ²=(μ_(1,3) ², μ_(P,3) ²) and σ₃ ²=(σ_(1,3) ², σ_(P,3) ²).

Step 306 includes summing the identified averages of the tool effect for the tools, or representative tool clusters, to determine a forecasted average tool effect. The trend forecasting module 26 may perform this step. Continuing the above example, the trend forecasting module 26 may sum the averages of IDDQ for the tools that processed the wafer and/or lot in the two stages and may sum the averages of P-delay for the tools that processed the wafer and/or lot in the two stages. In this example, the general equations may be as shown in equations (3) and (4) below, where M−1 is the stage number of the key process stage 12.

$\begin{matrix} {{\hat{\mu}}_{I} = {\sum\limits_{q = 1}^{M - 1}\;\mu_{I,k}^{q}}} & {{Eq}.\mspace{14mu}(3)} \\ {{\hat{\mu}}_{P} = {\sum\limits_{q = 1}^{M - 1}\;\mu_{P,k}^{q}}} & {{Eq}.\mspace{14mu}(4)} \end{matrix}$ More specifically for the example, the forecasted average tool effect may be shown as below in equations (5) and (6).

$\begin{matrix} {{\hat{\mu}}_{I} = {{\sum\limits_{q = 1}^{2}\;\mu_{I,k}^{q}} = {\mu_{I,2}^{1} + \mu_{I,3}^{2}}}} & {{Eq}.\mspace{14mu}(5)} \\ {{\hat{\mu}}_{P} = {{\sum\limits_{q = 1}^{2}\;\mu_{P,k}^{q}} = {\mu_{P,2}^{1} + \mu_{P,3}^{2}}}} & {{Eq}.\mspace{14mu}(6)} \end{matrix}$

Step 308 includes determining a root mean square (RMS) of the identified standard deviations of the tool effects for the tools, or representative tool clusters, to determine a forecasted standard deviation tool effect. The trend forecasting module 26 may perform this step. Continuing further with the above example, the trend forecasting module 26 may determine the RMS of the standard deviations of IDDQ for the tools that processed the wafer and/or lot in the two stages and may determine the RMS of the standard deviations of P-delay for the tools that processed the wafer and/or lot in the two stages. In this example, the general equations may be as shown in equations (7) and (8) below. {circumflex over (σ)}₁ =RMS(σ_(1,k) ^(q))  Eq.(7) {circumflex over (σ)}_(P) =RMS(σ_(P,k) ^(q))  Eq.(8) More specifically for the example, the forecasted standard deviation tool effect may be shown as below in equations (9) and (10).

$\begin{matrix} {{\hat{\sigma}}_{I} = {{{RMS}\left( \sigma_{I,k}^{q} \right)} = \sqrt{\frac{\left( \sigma_{I,2}^{1} \right)^{2} + \left( \sigma_{I,3}^{2} \right)^{2}}{2}}}} & {{Eq}.\mspace{14mu}(9)} \\ {{\hat{\sigma}}_{P} = {{{RMS}\left( \sigma_{P,k}^{q} \right)} = \sqrt{\frac{\left( \sigma_{P,2}^{1} \right)^{2} + \left( \sigma_{P,3}^{2} \right)^{2}}{2}}}} & {{Eq}.\mspace{14mu}(10)} \end{matrix}$

FIG. 6 is a method for dispatching the wafer and/or lot for a tuning process, as in Step 400 illustrated in FIG. 2. Step 402 includes prioritizing tools within a tuning process stage based on, at least in part, the forecasted trend of the wafer and/or lot. The dispatching control engine module 24 may prioritize the tools within the tuning process stage 16 based on the forecasted average and standard deviation of the tool effects for the tools that processed the wafer and/or lot. The tuning process stage 16 may provide data to identify which tools are in the tuning process stage 16 to the TCE determination module 22 by data flow 56. The TCE determination module 22 may then forward the data to the trend forecasting module 26 along with the average and standard deviation of the tool effect for the parameter(s) corresponding to the tools in the tuning process stage 16 by control flow 52. The trend forecasting module 26 may then provide the data for which tools are in the tuning process stage 16, the averages and standard deviations of the tool effects corresponding to those tools, and the forecasted average and standard deviation of the tool effects to the dispatching control engine module 24 by control flow 54. The dispatching control engine module 24 may also receive target information from the WAT/CP device 18 by the data flow 60.

By having the forecasted trend and the tool effects for the various tools in the tuning process stage, the dispatching control engine module 24 may prioritize the tools within the tuning process stage 16 to obtain a desired output of the tuning process stage 16. By knowing the forecast trend, a tool in the tuning process stage 16 that most appropriately compensates for these amounts may be assigned a higher priority. With the above example, based on an optimization comparing the forecasted trend {circumflex over (μ)}₁, {circumflex over (μ)}_(P), {circumflex over (σ)}₁, and {circumflex over (σ)}_(P) to the averages and standard deviations of the tool effect of each tool in the tuning process stage 16, i.e. stage-3 μ_(1,k) ³, σ_(1,k) ³, μ_(P,k) ³, and σ_(P,k) ³, to attain a target, tools in the tuning process stage 16 may be prioritized for the wafer and/or lot. The optimization may consider a lot independently to best achieve the desired target for the lot. The optimization may further consider all lots that are being processed by the system simultaneously to balance achieving the desired target and availability of tools in the tuning process stage.

With reference to FIGS. 7A and 7B, there are shown example results of a prioritization considering a lot that is being processed independently and of a prioritization considering all lots that are being processed simultaneously, respectively. In FIGS. 7A and 7B, there are shown various routings for Lot-1 through Lot-M between Stage-1 through Stage-(N−1), where Stage-(N−1) is a key process stage, such as key process stage 12. FIG. 7A shows the priority (Priority 1, Priority 2, etc.) assigned to the tools (Tool-1, Tool-2, etc.) in the tuning process stage N, such as the tuning process stage 16 in FIG. 1. Because each lot is considered independently in FIG. 7A, Tool-5 may be assigned the highest priority, Priority 1, for both Lot-1 and Lot-2 regardless of whether Tool-5 will be available or released when Lot-2 is available for processing. In FIG. 7B, Tool-5 is given a lower priority, Priority 2, compared to FIG. 7A, for Lot-2 because the prioritization considers all lots simultaneously and, thus, the availability of tools in Stage-N, the tuning process stage.

Referring back to FIG. 6, step 404 includes dispatching the wafer and/or lot to a tool in the tuning process stage based on the priority. The dispatching control engine module 24 may provide a dispatch control signal to the tuning process stage 16 by dispatching control flow 66 based on the priority assigned by the dispatching control engine module 24 to the tools in the tuning process stage 16. The dispatch control signal may direct to which tool the wafer and/or lot may be dispatched for processing. The tuning process stage 16 may therefore compensate the forecasted trend by having the wafer and/or lot processed by a tool that has a tool effect that compensates the forecasted trend. Referring to FIGS. 7A and 7B, each lot may be dispatched to the respective tool that has been assigned Priority 1 with regard to that lot. For example, in FIG. 7A, Lot-2 may be dispatched to Tool-5 in tuning process stage N, and in FIG. 7B, Lot-2 may be dispatched to Tool-7 in tuning process stage N.

Using an embodiment may allow a finished wafer to have a higher electrical performance quality than using previously known systems and methods. For example, the wafer may be manufactured nearer to a target because of the compensation control provided by an embodiment. Further, an embodiment may balance productivity by limiting downtime of tools or of lots and quality of the end product. Also, according to an embodiment, not only may the quality be increased, but a deviation of electrical performance between different wafers or lots may be decreased.

It should also be noted that the figures, particularly FIG. 1, illustrate a simplified system to clearly depict novel concepts of embodiments. A person having ordinary skill in the art will readily understand that such a system may comprise a multitude of stages. The system may similarly comprise multiple key process stages and multiple tuning process stages, although only one of each is depicted in FIG. 1. Further, the system may comprise other stages before, between, and/or after a key process stage and a tuning process stage. These other stages may be uncontrolled by an embodiment, but may be controlled by other acceptable methods, such as an Automatic Process Control (APC) system. For example, measurements from key in-line measurement device 14 may provide measurements to the in-line model module 20 by control flow 48 for use in an APC system.

Also, the different modules depicted in FIG. 1 may be implemented using computer program code in one or more general purpose computer or processor based system. Referring now to FIG. 8, a block diagram of a processor based system 70 is provided in accordance with an embodiment. The processor based system 70 is a general purpose computer platform and may be used to implement processes discussed herein. The processor based system 70 may comprise a processing unit 72, such as a desktop computer, a workstation, a laptop computer, or a dedicated unit customized for a particular application. The processor based system 70 may be equipped with a display 88 and one or more input/output devices 90, such as a mouse, a keyboard, or printer. The processing unit 72 may include a central processing unit (CPU) 74, memory 76, a mass storage device 78, a video adapter 82, and an I/O interface 84 connected to a bus 80.

The bus 80 may be one or more of any type of several bus architectures including a memory bus or memory controller, a peripheral bus, or video bus. The CPU 74 may comprise any type of electronic data processor, and the memory 76 may comprise any type of system memory, such as static random access memory (SRAM), dynamic random access memory (DRAM), or read-only memory (ROM).

The mass storage device 78 may comprise any type of storage device configured to store data, programs, and other information and to make the data, programs, and other information accessible via the bus 80. The mass storage device 78 may comprise, for example, one or more of a hard disk drive, a magnetic disk drive, or an optical disk drive.

The video adapter 82 and the I/O interface 84 provide interfaces to couple external input and output devices to the processing unit 72. As illustrated in FIG. 8, examples of input and output devices include the display 88 coupled to the video adapter 82 and the I/O device 90, such as a mouse, keyboard, printer, and the like, coupled to the I/O interface 84. Other devices may be coupled to the processing unit 72, and additional or fewer interface cards may be utilized. For example, a serial interface card (not shown) may be used to provide a serial interface for a printer. The processing unit 72 also may include a network interface 86 that may be a wired link to a local area network (LAN) or a wide area network (WAN) 92 and/or a wireless link.

It should be noted that the processor based system 70 may include other components. For example, the processor based system 70 may include power supplies, cables, a motherboard, removable storage media, cases, and the like. These other components, although not shown, are considered part of the processor based system 70.

Embodiments may be implemented on the processor based system 70, such as by program code executed by the CPU 74. A person having ordinary skill in the art will readily understand how methods according to embodiments, such as those described with respect to FIGS. 2 through 6 above, may be implemented by program code. Accordingly, explicit discussion herein is omitted.

Further, it should be noted that the modules in FIG. 1 may all be implemented on one processor based system 70, that each module may be implemented on a separate processor based system 70, or that a combination of modules may be implemented on various numbers of processor based systems 70. Communication between the different modules, such as data flow 64 and control flows 46, 52, and 54, may vary depending upon how the modules are implemented. If the modules are implemented on one processor based system 70, data may be saved in memory 76 or mass storage 78 between the execution of program code for different steps by the CPU 74. The data may then be provided by the CPU 74 accessing the memory 76 or mass storage 78 via bus 80 during the execution of a respective step. If modules are implemented on different processor based systems 70 or if data is to be provided from another storage system, such as a separate database, data can be provided between the systems 70 through I/O interface 84 or network interface 86. Similarly, data provided by the devices or stages may be input into one or more processor based system 70 by the I/O interface 84 or network interface 86. A person having ordinary skill in the art will readily understand other variations and modifications in implementing systems and methods that are contemplated within the scope of varying embodiments.

Although the present embodiments and their advantages have been described in detail, it should be understood that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the disclosure as defined by the appended claims. Moreover, the scope of the present application is not intended to be limited to the particular embodiments of the process, machine, manufacture, composition of matter, means, methods and steps described in the specification. As one of ordinary skill in the art will readily appreciate from the disclosure, processes, machines, manufacture, compositions of matter, means, methods, or steps, presently existing or later to be developed, that perform substantially the same function or achieve substantially the same result as the corresponding embodiments described herein may be utilized according to the present disclosure. Accordingly, the appended claims are intended to include within their scope such processes, machines, manufacture, compositions of matter, means, methods, or steps. 

What is claimed is:
 1. A method for semiconductor processing control, the method comprising: using at least one processor: identifying a key process stage from a plurality of process stages based on a parameter of processed wafers; forecasting a trend for a wafer processed by the key process stage and some of the plurality of process stages based on the parameter, wherein the forecasting the trend comprises: identifying a first plurality of tools that processed the wafer, the first plurality of tools being from the key process stage and the some of the plurality of processing stages, providing a statistical representation of a tool effect based on the parameter for each of the first plurality of tools, and determining the trend based on the statistical representation of the tool effect of each of the first plurality of tools; and dispatching the wafer to one of a second plurality of tools in a tuning process stage, wherein the one of the second plurality of tools is determined based on the trend.
 2. The method of claim 1 further comprising clustering some of a third plurality of tools within one of the plurality of process stages into a tool cluster.
 3. The method of claim 2, wherein the clustering comprises: providing a data set of measured results of the parameter of the processed wafers, wherein the data set comprises a plurality of subsets, each of the plurality of subsets corresponding to the measured results of some of the processed wafers processed by one of the third plurality of tools; determining a statistical representation of a tool effect for each of the third plurality of tools based on a respective corresponding one of the plurality of subsets; determining a pair-wise distance between respective statistical representations for a pair of the third plurality of tools; and clustering the pair of the third plurality of tools when the pair-wise distance is below a defined threshold.
 4. The method of claim 1, wherein the identifying the key process stage comprises: providing a data set of measured results of the parameter for the processed wafers, wherein the data set comprises a plurality of subsets, each of the plurality of subsets corresponding to the measured results of some of the processed wafers processed by one of multiple tools in each of the plurality of processing stages; determining an average tool effect and a standard deviation tool effect for each of the multiple tools in each of the plurality of processing stages based on a respective corresponding one of the plurality of subsets; determining an overall index for each of the plurality of processing stages based on the average tool effect and the standard deviation tool effect for each of the multiple tools in the respective one of the plurality of processing stages; and identifying the key process stage when the overall index for the key processing stage is above a threshold.
 5. The method of claim 4, wherein the overall index is based on a weighted average tool effect and a weighted standard deviation tool effect.
 6. The method of claim 1, wherein the statistical representation comprises an average tool effect and a standard deviation tool effect, wherein the determining the trend comprises: summing together the average tool effect for each of the first plurality of tools; and determining a room mean square of the standard deviation tool effect for each of the first plurality of tools.
 7. The method of claim 1, wherein the dispatching the wafer comprises: assigning a priority to each of the second plurality of tools based on the trend; and dispatching the wafer to the one of the second plurality of tools, wherein the one of the second plurality of tools has a high priority.
 8. The method of claim 7, wherein the assigning the priority is further based on an availability of each of the second plurality of tools.
 9. The method of claim 1, wherein the parameter includes a first parameter and a second parameter.
 10. A system for semiconductor processing, the system comprising: a processing line comprising a key process stage and a tuning process stage, the key process stage most affecting an electrical parameter of a finished product, and the tuning process stage being subsequent to the key processing stage in the processing line; a tool effect module operable on a processor and operable to determine tool effects on the electrical parameter for tools in the key process stage and for tools in the tuning process stage; an in-line model module operable on a processor and operable to identify the key processing stage by determining an average tool effect and standard deviation tool effect for each of the tools in each stage of the processing line based on measured results of parameters of processed wafers, determining an overall index for each stage based on the average tool effect and the standard deviation tool effect for each of the tools in the respective stages, and identifying the key process stage when the overall index for the key processing stage is above a predetermined threshold; a trend forecast module operable on a processor and operable to determine a trend of the electrical parameter of a wafer that has been processed through the key process stage; and a dispatch control module operable on a processor and operable to determine a tuning tool in the tuning process stage that optimally compensates for the trend of the electrical parameter of the wafer and to dispatch the wafer to the tuning tool.
 11. The system of claim 10, wherein the tool effect module is further operable to cluster tools in at least one stage of the processing line based on the tool effects.
 12. The system of claim 11, wherein the tool effect module is operable to cluster the tools in the at least one stage by determining statistical representations of the tool effects based on measured results of processed wafers processed by the tools in the at least one stage, determining a pair-wise distance between respective statistical representations, and clustering the tools when the pair-wise distance is below a defined threshold.
 13. The system of claim 10, wherein the trend is based on a routing history of the wafer.
 14. The system of claim 13, wherein the trend is based on a statistical representation of a tool effect based on the electrical parameter.
 15. The system of claim 10, wherein the dispatch control module is operable to determine the tuning tool by assigning a priority to each tool in the tuning process stage, the tuning tool having a highest priority of the tools in the tuning process stage.
 16. The system of claim 15, wherein the priority of each tool is based on an availability of each tool in the tuning process stage.
 17. The system of claim 10 further comprising an in-line model module operable to: receive a data set for measured results for the electrical parameter of processed wafers, the data set comprising subsets, each subset corresponding to one tool of multiple tools in the processing line; determine a residual model for each subset; determine a residual vector for each subset, a residual vector entry being based on the residual model and one of the measured results of the respective subset; determine a residual average and a residual standard deviation of the residual vector for each subset, such that each of the multiple tools has a corresponding residual average and residual standard deviation; for each stage of the processing line, determine an overall index based on the residual average and residual standard deviation for each of the multiple tools in the respective stage; and identify at least one stage of the processing line as the key process stage when the at least one stage has a corresponding overall index greater than a threshold.
 18. The system of claim 10, wherein the trend forecast module is operable to: identify routed tools in stages of the processing line through the key process stage that processed the wafer; identify a residual average and a residual standard deviation corresponding to the electrical parameter corresponding to the routed tools; sum together the residual average corresponding to each of the routed tools to obtain a trend average; and determine a root mean square (RMS) of the residual standard deviation corresponding to each of the routed tools to obtain a trend standard deviation. 